Operation characteristics of semiconductor devices vary due to a change in an environment of use, an aging change, or the like such as supply voltage or temperature. For this reason, the following countermeasure is needed. That is, an abnormal operation caused by use of a semiconductor device at a temperature beyond an operation guarantee temperature range or the like is detected in advance. Then, operation of the device is changed according to a location (failure location) at which the abnormal operation has occurred. In related art semiconductor devices which do not include a function of identifying a failure location, operation at a time of failure cannot be changed according to the failure location.
As a configuration for allowing detection of an integrated circuit device that is about to be broken before occurrence of a failure, Patent Document 1 discloses a configuration including an evaluation circuit in a semiconductor integrated circuit device. The evaluation circuit is provided independent of a main body circuit that achieves a primary function. A clock signal having a frequency higher than a clock signal for operating the main body circuit is supplied to the evaluation circuit for operation. In Patent Document 1, the evaluation circuit is operated at the clock frequency higher than the clock frequency for the main body circuit. Thus, the evaluation circuit that operates at the higher clock frequency deteriorates earlier than the main body circuit. This deterioration normally appears in the form of a delay of an output signal of the evaluation circuit. Then, by providing a deterioration detection unit that detects this delay, the deterioration of the evaluation circuit is detected.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2005-277087A